1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device whose memory cells can be tested at high speed.
2. Description of the Related Art
In recent semiconductor memory devices, there is a demand for testing memory cells at high speed in accordance with remarkable increases in memory capacity. However, since the speed of an external clock signal supplied from the outside of the memory devices cannot be increased, a phase-locked loop (PLL) is installed in the device to make the internal circuit operate at high speed (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-329000). In this case, when testing a memory, the input/output circuit (IO) does not operate at high speed, therefore a high frequency signal cannot be applied to the memory from outside. In other words, high-speed testing cannot be performed. In particular, in memory-combined LSIs in which a memory circuit and logic circuit are combined in a single semiconductor substrate, the memory macro that constitutes the memory circuit is demanded to operate at very high speed. However, in many cases, it cannot be tested from the outside whether the memory macro can operate at high speed. Furthermore, a high-speed memory tester is very expensive, therefore impractical.
A conventional semiconductor memory device example will now be described.
FIG. 1 is a block diagram illustrating a memory macro incorporated in a conventional memory-combined LSI. A memory macro 1-0 comprises a memory core 1-1 and test input/output data control circuit 1-2. The memory core 1-1 has a plurality of memory cells. A write command WTp, read command RDp, clock CLKp and address (not shown) are input to the memory core 1-1. Further, the test input/output data control circuit 1-2 is connected to data input lines DI<0:4n+3> (n: a natural number including 0), and to data output lines DO<0:4n+3>.
Upon receiving the write command WTp, the memory macro 1-0 writes the data, input to data input lines DI<0:4n+3>, to memory cells of an address corresponding to the data input lines. Further, upon receiving the read command RDp, the memory macro 1-0 reads data from the memory cells of the corresponding address, and outputs the read data from data output lines DO<0:4n+3>.
The memory macro 1-0 incorporated in a memory-combined LSI has a large number of data input/output lines. In a standard test, a test is performed using test data input lines TDI<0:3> and test data output lines TDO<0:3> (in this case, the simultaneous use of test data of 4 bits is assumed). The test input/output data control circuit 1-2 controls the input/output of test data. Since the number of standard data input/output lines is 4(n+1) and the number of test data input/output lines is 4, the standard data input/output lines are divided into a number (n+1) of blocks to be accessed. A block selection address TBS<0:m> is a signal for selecting a particular one of the number (n+1) of blocks. “m” is also a natural number including 0, and “m” and “n” satisfy 2m+1≧n+1.
The test data input lines TDI<0:3> for receiving test data from the outside and the test data output lines TDO<0:3> for outputting test data to the outside are connected to the test input/output data control circuit 1-2. Further, a clock CLKp is input to the test input/output data control circuit 1-2.
Referring to FIG. 8, signal generation timing for testing the memory macro shown in FIG. 1 will be described. Signals SELCYCLEp<0:3> and RTSp are irrelevant to this explanation, therefore may be ignored. A clock (signal) CLK is an external clock supplied from the outside. A test command TCMD is not shown in FIG. 1, and is a signal obtained by multiplexing the read command RDp and write command WTp. The test command TCMD indicates the timing of input of the write command WTp or read command RDp. One latency (period), which corresponds to one pulse (cycle) of the clock CLK, is required for capturing each command. This is represented by a command CMD. A read command RD0, write command WT1 and read command RD2 are sequentially input at every fourth cycle of the clock CLK. Addresses are input at the same timing as the commands (this is not shown).
Data is input six clocks later than the input of a command. When the read command RDp is input, data of four cycles is output. When the write command WTp is input, data of four cycles is input. The test data input to the test data input lines TDI six to nine cycles after the input of the read command RD0 is used as expected value data EXP. Data items D0, D1, D2 and D3 as the expected value data EXP are compared with data items R0, R1, R2 and R3 as output data DO, respectively. As shown in FIG. 8, the comparison results are output two cycles later than the start of comparison. In the case of FIG. 8, only the data R1 of the second cycle is not equal to the comparison data (Fail), and the other data items R0, R2 and R3 are equal to the respective comparison data items (Pass).
To test the internal memory of the semiconductor memory device shown in FIG. 1, using an internal clock four times faster than a slow (low-frequency) external clock, it is needed to input data at a speed four times faster than the external clock, which is impossible. Further, it is needed to output data at the speed four times faster than the external clock. Alternatively, it is needed to repeat the same test four times to output data at different points in time.